Complete Integration
A complete system-on-chip integrating every IP core in our portfolio into a single, production-ready platform. RISC-V processor with post-quantum cryptography acceleration, hardware security module, error-protected memory, and full peripherals — all connected through a high-performance crossbar interconnect.
12 IP cores in one SoC: RISC-V processor, ML-KEM-768, HSM, SRAM, ROM, DMA, crossbar interconnect, UART, SPI, clock/reset management, pad ring, and debug interface.
Main (80 MHz), PQC (80 MHz, gateable), Peripheral (40 MHz, gateable), and Debug (10 MHz, independent) with safe clock domain crossing between all domains.
42 signal pads plus 16 power/ground pads in a full pad ring with ESD protection, level shifting, and configurable drive strength for every interface.
Architecture
A complete quantum-safe computing platform from processor to pad ring. The RISC-V processor with custom PQC instruction extensions drives the system through a 4-master, 8-slave crossbar interconnect.
The ML-KEM-768 accelerator provides hardware-accelerated NIST FIPS 203 key encapsulation, while the HSM module delivers FIPS 140-3 Level 3 key management with a 64-slot secure vault. ECC-protected SRAM and integrity-verified boot ROM provide reliable storage, and the DMA controller enables high-throughput data movement without CPU overhead.
UART and SPI peripherals provide external communication, while the debug interface enables full hardware debugging. A 4-domain clock/reset management unit, complete pad ring, and dedicated tamper and entropy inputs round out the system.
| Component | Details |
|---|---|
| Processor | RISC-V RV32IMC, 5-stage pipeline, custom PQC extensions |
| PQC Engine | ML-KEM-768 (FIPS 203) with hardware acceleration |
| Security | HSM with AES-256, SHA-3, key vault |
| Memory | 8 KB SRAM (ECC) + 8 KB ROM (integrity-verified) |
| DMA | 4-channel scatter-gather engine |
| Interconnect | AXI4-Lite 4M × 8S crossbar |
| Peripherals | UART + SPI + GPIO |
| Debug | RISC-V Debug Specification compliant |
System Map
8 bus slots decoded by the crossbar interconnect, each providing an 8 KB address region for its assigned peripheral.
| Slot | Peripheral | Size | Status |
|---|---|---|---|
| Slot 0 | ML-KEM-768 Accelerator | 8 KB | Active |
| Slot 1 | HSM PQC Module | 8 KB | Active |
| Slot 2 | TLS/IPsec Offload | 8 KB | Reserved |
| Slot 3 | Root of Trust PQC | 8 KB | Reserved |
| Slot 4 | SRAM Controller (ECC) | 8 KB | Active |
| Slot 5 | ROM Controller (Integrity) | 8 KB | Active |
| Slot 6 | UART Controller | 8 KB | Active |
| Slot 7 | SPI Controller | 8 KB | Active |
Clocking
4 independent clock domains with safe domain crossing and power gating for energy-efficient operation.
| Clock Domain | Frequency | Type | Consumers |
|---|---|---|---|
| Main | 80 MHz | Always-on | Processor, Crossbar, SRAM, ROM, DMA |
| PQC | 80 MHz | Gateable | ML-KEM-768, HSM PQC |
| Peripheral | 40 MHz | Gateable | UART, SPI, GPIO |
| Debug | 10 MHz | Independent | Debug Interface |
I/O
58 total pads: 42 signal + 16 power/ground with ESD protection.
| Edge | Signals | Count |
|---|---|---|
| Bottom | Clock, Reset, Power-On Reset, Debug Interface | 7 signal + 4 power |
| Right | UART TX/RX, SPI MOSI/MISO/SCK/CS | 10 signal + 4 power |
| Top | GPIO (16 pins) | 16 signal + 4 power |
| Left | Tamper, Entropy, IRQ, Status, Debug, Boot Select, Spare | 9 signal + 4 power |
| Total | 42 signal + 16 power = 58 pads |
Specifications
| Parameter | Specification |
|---|---|
| Process Node | 180 nm |
| Die Size | 3.5 × 3.5 mm (12.25 mm²) |
| Core Area | 3.2 × 3.2 mm (10.24 mm²) |
| Gate Count | ~50K gates equivalent |
| Operating Frequency | 80 MHz (main clock) |
| Core Voltage | 1.8 V |
| I/O Voltage | 3.3 V |
| Power (Active) | ~15 mW |
| Power (Idle) | ~2 mW |
| Total I/O Pads | 58 (42 signal + 16 power) |
Components
Each core is available independently or as part of the integrated SoC platform.
NIST FIPS 203 lattice-based Key Encapsulation Mechanism with hardware acceleration for post-quantum key exchange.
View Details → SecurityFIPS 140-3 Level 3 Hardware Security Module with comprehensive cryptographic operations and secure key vault.
View Details → Processor5-stage RV32IMC processor with custom PQC instruction extensions and dual bus masters.
View Details → InterconnectFull crossbar interconnect with 4 masters and 8 slaves and round-robin arbitration.
View Details → Memory8 KB SRAM with SECDED error correction and built-in self-test for reliable data storage.
View Details → Data Engine4-channel scatter-gather engine for high-throughput data movement without CPU overhead.
View Details → EntropyTrue quantum random number generation with photonic entropy and continuous self-certification.
View Details → Future-ProofReconfigurable cryptographic engine with runtime algorithm switching and CNSA 2.0 compliance.
View Details → PrivacyCompute on encrypted data without decryption for privacy-preserving AI and confidential analytics.
View Details →Get the complete SoC platform with all IP cores, integration documentation, and evaluation support from our engineering team.