Error-Protected Memory
Reliable, error-protected memory for security-critical applications. Hardware error correction transparently fixes single-bit faults and detects double-bit errors, while built-in self-test ensures manufacturing and runtime integrity.
Hardware SECDED (Single Error Correct, Double Error Detect) ECC transparently corrects single-bit memory faults on every read. No software intervention required — data integrity is maintained automatically.
March C- built-in self-test algorithm for comprehensive stuck-at fault detection. Runs at manufacturing test and can be triggered at runtime for periodic memory health validation.
8 kilobytes of ECC-protected on-chip SRAM with standard bus interface. Ideal for cryptographic key storage, intermediate computation buffers, and secure data scratchpad.
Specifications
| Parameter | Value |
|---|---|
| Capacity | 8 KB |
| Data Width | 32 bits |
| ECC Type | SECDED (Hamming) |
| Error Correction | Single-bit (transparent) |
| Error Detection | Double-bit (flagged) |
| Self-Test | March C- algorithm |
| Bus Interface | Standard SoC bus |
| Target Frequency | 80 MHz |
Contact our team for evaluation access or custom memory configurations for your security-critical designs.